The semiconductor industry continues to yield integrated circuits (ICs) of increasing density in order to reduce their overall required chip space. An IC comprises a plurality of conductive layers stacked one on top of another between dielectric insulators on a substrate. For ease of design and debugging, a common fabrication method is to implement the functional portions of the chip in separate blocks. Because each functional block may not be identical, this method typically results in conductive layer density variations between blocks. Furthermore, typical layouts include empty space between functional blocks. Accordingly, the density variations between different areas on a conductive layer may vary widely.
With new fabrication technologies such as chemical mechanical polishing, the functional block approach to chip design is problematic. Chemical mechanical polishing is a method used for planarizing a semiconductor wafer. The chemical mechanical polishing method rotates a polishing platen coated with a slurry solution at a constant speed over the surface of a semiconductor wafer in order to provide uniform thickness. However, when the chip layer being polished is not uniform in density, the conductive material in low density areas is eroded more quickly than the material in high density areas. For example, the metal lines at the edges of a functional block that reside adjacent to one of the empty spaces between functional blocks are polished down more quickly than metal lines that that are surrounded by other metal lines in close proximity, resulting in non-uniform metal thickness across a given chip layer.
Accordingly, a need exists for a method for increasing conductive layer density uniformity without requiring a drastic change in design or manufacturing process methodology.